1. Field of the Invention
This invention relates to semiconductor integrated circuits and, more particularly, to a circuit for outputting a signal with a constant period by means of an oscillator circuit or a frequency divider circuit connected to the oscillator circuit.
2. Description of the Related Art
Dynamic random access memories (DRAMs) are broadly used as cells (memory cells) for storing information. The DRAM, for holding information depending upon the presence or absence of storage charge on the capacitor, has a feature to gradually release the written charge and lose information as time elapses. In order to hold information at all times, there is a need to periodically read and rewrite the content on the memory cell. This operation is called refresh. On the DRAM, refresh is possible with external input. The refresh operation at a constant time interval eliminates the possibility of information erasure. Meanwhile, the DRAM has a self-refresh function to automatically make a refresh operation at a constant time interval by means of an internal timer.
The interval of refresh operation is determined by a discharge time of the charge written on the memory cell. Generally, discharge time is shorter at high temperature as compared to that at low temperature. For this reason, it is the conventional practice to set a refresh operation interval in self-refresh mode at a sufficiently short time not to erase information even at high temperature, thus making the refresh operation interval constant to a possible extent regardless of temperature. As a result, the interval of the refresh operation at low temperature can become unnecessarily short.
Recently, from the demand for the products reduced in power consumption, there is a need for an approach that the consumption power at low temperature is reduced by increasing the refresh interval.
For example, Japanese Patent Kokai No. 5-299982 (Patent Document 1), page 3, FIG. 1, discloses that a resistance element is provided in a CMOS (complementary-type MOS transistor) of a ring oscillator circuit, as an resolution for the situation that oscillation period is increased at high temperature region by the on-resistance of a transistor resulting in increased DRAM refresh period. Patent Document 1, although aiming mainly at outputting an oscillation period with a constant period without dependent upon temperature, discloses the capability of providing a ring oscillator circuit having an oscillation period decreasing with increasing temperature by the use of such a resistance element that resistance value decreases with increasing temperature.
By incorporating such a resistance element that resistance value decreases with increasing temperature in an oscillator circuit for adjusting a capacitor charge/discharge time by the magnitude of resistance value of the resistance element, it is possible to provide a ring oscillator circuit having a feature that oscillation period is short at high temperature but long at low temperature.
FIG. 1 is the simplest configuration example of such a ring oscillator circuit. An oscillator circuit 400 is configured by the series connection in a sequential ring form of an inverter 402 at the first stage including one delay circuit 426, three middle-stage inverters 404, 406 and 408, and an inverter 410 at the last stage. Herein, in order to connect the oscillator circuit 400 to an outside, the final-stage inverter 410 is configured by a NAND circuit. The NAND circuit 410 has two input terminals to which connected are an output terminal of the preceding-stage inverter 408 and an external terminal to be inputted by a binary signal ST. The NAND circuit 410 is under control of inputting the signal ST. Assuming that one binary value is “1”, i.e. “high level” and the other is “0”, i.e. “low level”, when the signal ST is at high level, the oscillator circuit assumes an on-state and the NAND circuit 410 operates as an inverter.
The inverter 402 for the first stage has a transistor series circuit 424 having a PMOS transistor (referred also to as PMOST) 414 and an NMOS transistor (referred also to as NMOST) 416 connected in series at their main current passages, and the delay circuit 426 connected to the transistor series circuit 424 and for providing a delay to an output of the inverter 402. This delay circuit 426 is configured by a temperature-dependent resistance element 418 and a capacitor 420. Incidentally, 412 and 422 represent nodes.
The ring oscillator circuit 400 has an oscillation period greatly varying depending upon the time required in discharging the charge stored on the capacitor 420. When the temperature-dependent resistance element 418 increases its resistance value, the flowing current decreases to increase the time required for discharge, proportionally increasing the oscillation period. Accordingly, on the ring oscillator circuit 400, because the resistance value of the temperature-dependent resistance element 418 decreases with increasing temperature, the oscillation period is shorter as temperature rises.
FIG. 2 is a graph outlining the relationship between an oscillation period outputted by the ring oscillator circuit 400 shown in FIG. 1 and a temperature.
The vertical axis represents a common logarithm value of a relative value at each temperature when the oscillation period at 80° C. is taken 1. The horizontal axis denotes a temperature (unit: ° C.).
The refresh period, required for the DRAM to hold data, empirically increases to approximately 1.4 times as temperature lowers by 10° C. Consequently, the graph shows the case assuming that, the temperature characteristic of the temperature-dependent resistance element 418 is such that the resistance value increases to 1.35 times as the temperature lowers by 10° C.
Because oscillation period is proportional to the magnitude of resistance value of the temperature-dependent resistance element 418, as temperature rises the resistance value decreases to shorten the oscillation period. Conversely, as temperature lowers the resistance value of the temperature-dependent resistance element 418 increases to increase the oscillation period. The DRAM refresh period at low temperature can be increased by the increased oscillation period. This can reduce consumption power.
Such a ring oscillator circuit, having a charge/discharge circuit built with a capacitor and resistance element, is quite useful because of its resistance to MOS transistor manufacturing variations and to power voltage fluctuations and of its simple circuit structure.
However, in the temperature-dependent resistance element 418 of the ring oscillator circuit 400, the resistance value continues to lower as temperature lowers. Accordingly, there is no maximum value in the oscillation period outputted by the ring oscillator circuit 400.
Accordingly, because the refresh period increases as temperature lowers, memory test is required over a broad temperature range. When to take a long refresh interval in the memory test under the self-refresh mode (i.e. memory test on operating the internal timer), test must be conducted at low temperature. Particularly, for a test at 0° C. or lower, because there is an apparatus that the moisture in air freezes to raise a problem, an expensive test apparatus is required to prevent this.
Meanwhile, in the DRAM memory cell, there are some route to leak the charge stored on the capacitor. In most cases, the leak current increases with increasing temperature. Rarely, there exists a memory cell having a route where leak current does not decrease even at low temperature because of microscopic defects or the like. In the oscillator circuit using a resistance element having a resistance value not changing on temperature, because a refresh interval is set required in a high temperature region, there is no need to exclude such memory cells as defective cells.
However, where using a conventional ring oscillator circuit having a resistance element having a resistance value increasing with increasing temperature, oscillation period increases at low temperature. The memory cells, having routes not decreasing leak current even at low temperature as in the above, are all excluded and replaced with spare memory cells (redundant cells). This lowers the yield in the manufacture of semiconductor integrated circuits.
Consequently, in case a maximum value can be set on the oscillation period increasing with decreasing temperature, test is not required at low temperature. Furthermore, in case a maximum value of oscillation period can be set, it is possible to reduce the replacing number of memory cells having routes not decreasing leak current even at low temperature as in the above, with redundant cells. This can improve the yield in the manufacture of semiconductor integrated circuits.
There is disclosed a method for setting a maximum value on oscillation period, for example, in Japanese Patent Kokai No. 5-307882 (Patent Document 2). In this Patent Document 2, a temperature detecting circuit is formed by the oscillation period of a CR oscillator circuit having a resistance element possessing a positive temperature characteristic. In this temperature detecting circuit, temperature region is divided into three, to change the outputs between the temperature regions. With the outputs, the frequency dividing period by the frequency divider circuit or the oscillation period by the ring oscillator is adjusted and used for DRAM refresh period.
However, in the method shown in Patent Document 2, the oscillation period by the ring oscillator abruptly varies at a temperature switching the output of the temperature detecting circuit.
In the circuit of Patent Document 2, the oscillation period is not in a straight line having a nearly constant inclination as haven on the graph of FIG. 2. The oscillation period assumes nearly constant in certain three temperature ranges set continuously. However, the oscillation period, because of abruptly varying at a temperature switching the oscillator circuit, assumes an oscillation characteristic varying stepwise.
Depending upon at what temperature the two switch points are set, the characteristic of oscillation period is greatly different. Hence, there is difficulty in determining the same. In order to reduce the memory cells replaced with redundant cells by a memory test, there is a necessity to suitably adjust the switching temperature. This makes oscillator circuit design quite difficult.
Consequently, there is a demand for an oscillator circuit having a temperature characteristic that the oscillation period is short at high temperature but long at low temperature and, moreover, allowed to be set with a maximum value of oscillation period.
Furthermore, in order to smoothen the adjustment for an oscillation period against temperature change, there is a demand for an oscillator circuit that can suppress an abrupt change of oscillation period in the usual-service temperature range.
Therefore, the inventor of the present invention has concluded that, by connecting the different resistances of resistance elements in parallel, oscillation period moderately varies such that it is short at high temperature but long at low temperature and, moreover, a maximum value of oscillation period can be set in a low temperature region.